With increasing popularity of electronic devices, such as computers, smart phones, mobile devices, server farms, mainframe computers, and the like, the demand for more and faster data is constantly growing. To handle and facilitate voluminous data between such electronic devices, high speed NV memory devices are typically used. A conventional type of NV memory device, for example, includes flash memory.
The flash memory, in one example, is an electronic NV computer storage device capable of maintaining, erasing, and/or reprogramming data. The flash memory can be fabricated with several different types of integrated circuit (“IC”) technologies such as NOR or NAND logic gates with, for example, floating-gate transistors. Depending on the applications, a typical memory access of flash memory can be configured to be a block, a page, a word, and/or a byte.
The structures and/or characteristics of flash memory cell exhibit characteristics similar to those of volatile memory circuitry. In flash memory, each memory cell, for example, resembles basic structure of a standard MOSFET, except that the flash memory cell contains at least one floating gate (“FG”) transistor which has two gates instead of one gate. On top of FG transistor is a control gate (“CG”) wherein below the CG, an FG is situated. An FG is typically insulated by one or more oxide or insulating layers, and is interposed between the CG and the MOSFET channel. Since the FG is electrically isolated by its insulating layer, any electrons that are trapped inside of the FG may last for a long period of time without substantially discharging.
When an FG holds a charge, it screens or partially cancels electric field generated by the CG. The CG is used to apply the threshold voltage (“Vt”) to the cell for memory access. Note that higher voltage is typically required at the CG to conduct the channel. During a read-out operation, a voltage such as Vt is applied to the CG to make the channel to be conductive. Upon sensing a current flowing through a MOSFET channel, a binary code or value can be read and a corresponding stored data is reproduced. In a multi-level cell device which stores more than one bit per cell, the amount of current flow is sensed in order to determine a level of charge which corresponds to a binary value stored in the FG.
A drawback, however, associated with a typical flash memory device is loss of charge prematurely due to certain environmental conditions, such as read disturb, read error, aging, inter-cell interference, and the like. If the storage controller fails to intervene in time, the loss of charge in the FG can lead to data loss and/or unusable or unrecoverable error-prone data. The read disturb, for example, may occur when a neighboring cell has been accessed. Reading NAND based flash memory, for instance, can cause nearby cells in the same memory block to dissipate their charges prematurely. To reduce premature loss of charge, a conventional approach is to refresh stored data based on certain conditions such as number of read times.